High Performance Using AES Algorithm in Cryptographic Application with Large 256-Bit Data Input

Abstract

Cryptography is very important now-a-days for data security and integrity as the ecommerce and internet applications has increased. But, it has least importance in many cases because of extra memory and other requirements needed for the implementation. The main aim of this work is to implement Advanced Encryption Standard (AES) Encryption using Verilog. To protect data like electronics, cryptographic algorithms are used. The digital information can be encrypted and decrypted by the block cipher of AES algorithm. It can be implemented with the key length 128, 192, 256 bits. Each round of encryption associated with delay can be reduced by AES parallel design. For storing plain text, keys, and intermediate data, we construct two specific register banks, Key-Register and State-Register. Shift-Rows are inserted into the State- Register to save space. We build an efficient 8-bit block for Mix-Columns with four internal registers that take 8-bit and send out 8-bit to adapt the Mix-Column to an 8-bit data stream. For the key expansion and encryption phases, shared optimized Sub-Bytes are also used. We consolidate and simplify various Sub-Bytes to make them more efficient. The clock gating method is used in the design to decrease power consumption. This study provides a 256-bit AES architecture based on Image Cryptography. This design is built-in Verilog HDL on an FPGA XC3S 200 TQ-144, simulated using Modalism 6.4 c, and synthesized with the Xilinx tool.