Main Article Content
A finite impulse response (FIR) filter is an essential component of any DSP and communication system. The adder and multiplier are two important components of filter architecture. Different adders and multipliers are available in digital circuits, but designing efficient filters requires an efficient adder and multiplier design. To achieve effective computation, the various existing functions of adders are classified, such as the carry select, ripple carry adder, which consumes more area, delay, and power. A novel carry save adder is combined with a structured Wallace tree multiplier and implemented into the digital filter to improve the efficiency of digital design. This novel carry save adder is built with majority logic and implemented in a digital FIR filter. This modified adder and multiplier overcomes the existing drawbacks. It is implemented using Verilog HDL. Compared to other adder techniques, the proposed majority logic produces optimal solutions. This new technique uses less power, has a delay-free carry circuit, and has fewer gate counts.